The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective when applied to a semiconductor integrated circuit device equipped with a SRAM (i.e., Static Random Access Memory).
The SRAM is disclosed as a volatile semiconductor device on pp. 48 to 51 of IEDM (i.e., International Electron Devices Meeting) Technical Digest, December, 1988, for example. In a SRAM of this type, a memory cell for storing information of 1 [bit] is arranged at each of intersections between complementary data lines and word lines.
The memory cell is composed of a flip-flop circuit and two transfer MOSFETs (i.e., Metal Oxide Semiconductor Field Effect Transistors). Each transfer MOSFET has its one semiconductor region connected with the input/output terminal of the flip-flop circuit and its other semiconductor region connected with a respective one of a pair of complementary data lines. Each of the transfer MOSFETs has its gate electrode connected with a word line so that its conduction and nonconduction states are controlled by the word line. The flip-flop circuit is constructed, as an information latching portion, of two drive MOSFETs and two load MOSFETs. The drive MOSFET has its drain region connected with one semiconductor region of one transfer MOSFET and its source region connected with a reference voltage line (i.e., a source line). The gate electrode of the drive MOSFET is connected with one semiconductor region of the other transfer MOSFET. The load MOSFET has its drain region connected with one semiconductor region of one transfer MOSFET and its source region connected with a supply voltage line (i.e., a source line).